FPGA-Based Design of Controller for Sound Fetching from Codec Using Altera DE2 Board

ABSTRACT— The trend in hardware design is towards implementing a complete system, intended for various applications, on a single chip. In order to implement the any speech application in Altera DE2 board a controller is designed to control the CODEC and acquire the digital data from it. This paper presents an experimental design and implementation of the controller using the specification given by the Philips for I2C protocol & DSP mode of operation of CODEC on cyclone-II EP2C35F72C6 FPGA in Altera DE2 board . A controller was designed using VHDL language, which performs the two operations: I2C protocol operation to drive the Wolfson Codec WM8731, sound fetching from Wolfson Codec WM8731 to FPGA in DSP mode. Altera Quartus II 9.0 sp2 web Edition is used for the synthesis of the VHDL logic on FPGA and ModelSimAltera 6.5b (Quartus II 9.1) Starter Edition is used for the simulation of VHDL logic. Three modules have been created in the design: the I2C bus controller, virtual sound fetcher, and the clock module. The FPGA communicates with the Wolfson via the I2C (Inter-Integrated Circuit) protocol using two pins: 'SDIN' (the data line), and 'SCLK' (the bus clock). I2C bus controller modifies internal settings of Codec, de-mute the microphone input, boost the microphone volume, and change the default sound path (so that the microphone is given priority over other inputs). After the codec digitalizes the input it put the digital data on digital audio interface, to fetch the data on DACDAT of codec form digital audio interface DSP mode of operation of codec is used in the design. DACDAT is the formatted digital audio data stream with left and right channels multiplexed together. DACLRC (alignment clock) and BCLK (synchronization clock) is used to fetch the data on DACDAT this data can be use for any sound application. Clock module is design to generate different clock requirement for the controller.